12/7/2023 0 Comments Positive d latch timing diagram(CLK)' is formed from CLK after a delay equivalent to an inverter delay. Please refer to figure 6 below for the illustration of this. So, the hold time for Data is one inverter delay minus transmission gate delay. Assuming CLK' takes one inverter delay, input transmission gate will close after one inverter delay only. This server as the hold time for the latch. Similarly, if we do not want the data to propagate to output, it must not cross input transmission gate so that it does not disturb the present state of the latch. Figure 5 below shows the setup time for the latch. So, setup time of the latch involves the delay of input transmission gate and the two inverters. This time is such that it goes into the memory of latch i.e., before input transmission gate closes, Data should traverse both the inverters of the loop. If we want the data to be propagated properly to the output, then Data should be stable for atleast some time before closing of the input transmission gate. Let us go into the details of what latch setup and hold time should be for transmission gate latch. So, there are setup and hold timing arcs between data and enable pins of a latch. This relationship can be modelled as setup and hold arcs. To make things more deterministic, we impose a certain condition that Data should not toggle when Enable is getting de-asserted. Relation between Data and Enable: If Data toggles very close to the closing edge of Enable, then, there might be a confusion as if its effect will be propagated to output or not (as discussed later in this post).Only then, the effect of input propagated to output So, in latches, there exists a timing arc from Enable to Out.įigure 3:When data changes during enable is in de-asserted state, output waits for the enable to assert. As figure 3 shows, Data had become stable a lot earlier, but out toggled only when enable became asserted. When this happens, latch waits for Enable to be asserted, then, follows the value of Data. Out changes with Enable: This happens when Data at input changes when Enable is in its de-asserted state.The latch is, thus, said to have a timing arc from Data to Out. This scenario is depicted in figures 1(b) and 2(b) above wherein out is shown toggling when Data toggles. When this happens, Out follows Data as there is a direct path between Data and Out when Enable is '1'. Out changes with Data: This happens when enable is in its asserted state (for example, for a positive level latch).Latch timing arcs: Data can propagate to the output of the latch in two ways as discussed below: Negative level-sensitive latch: A negative level-sensitive latch follows the input data when enable is '0' and keeps its output when input is '1'.įigure 2(a): Negative level- Figure 2(b): Timing waveform for a negative level- sensitive latch sensitive latch
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